Key features include
Wide range of IEEE 1149.1 test options (interconnect, shorts, opens, TAP, IDCODE, Register Length, and more), ATPG with pin-level diagnostics, cluster testing for non-jtag FLASH and memory devices, DFT reporting, BSDL verification, JTAG test simulation, automatic handling of multiple scan chains, interactive 'pin-toggle' mode, test scripting, Labview interface, and a straightforward GUI that guides new users through test development process. Tests are applied through inexpensive JTAG programming cables from Xilinx, Lattice, Altera and Insight Electronics.
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